In electronic system-in-package (or package-in-package) technology, a single package comprises one or more dice, where one or more of these dice are in their own individual packages. An example is provided in FIG. 1. FIG. 1 is a simplified, plan view (not to scale) illustration of a flip chip stacked module package. A die 102 is flip chipped, with its active side facing a package substrate 104. In the flip chip process, also formally called the Controlled Collapse Chip Connection (C4) evaporative bump process, conductive bumps (106) are formed and soldered to pads on the active side of the die 102. The solder bumped die 102 is then placed face down onto matching bonding pads on the package substrate 104, which may be a multilayer organic substrate. The assembly is reflowed so that the conductive bumps 106 are soldered to pads on the package substrate 104 so as to provide electrical connection between the active side of the die 102 and the package substrate 104. The conductive bumps 106 also provide a load bearing link between the die 102 and the package substrate 104. Usually, the conductive bumps comprise solder. The package substrate 104 includes electrical interconnects so that the conductive bumps 106 are electrically connected to at least some of a plurality of package contacts 108.
Attached to the backside of the die 102 is a package 110. This is a wirebond package, where a die 112 is attached to a package substrate 114, and electrical connection is provided by way of wirebonds from the active side of the die 112 to pads on the package substrate 114. As an example, one such wirebond, labeled 116, is shown. Wirebonds from pads on the outer side of the substrate package 114 provide electrical connection to the package substrate 104. For example, one such wirebond, labeled 118, is shown. Attached to the package 110 is a die 120, which is wirebonded to the package substrate 104. For example, one such wirebond, labeled 122, is shown.
An epoxy resin, sometimes referred to as an underfill, is usually applied to help compensate for the difference in the coefficient of thermal expansion (CTE) between the die 102 and the package substrate 104, and to prevent moisture damage. The assembly may also be capped with a liquid epoxy for further protection, resulting in the final system-in-package 124.
For some applications, the die 102 may comprise digital logic circuits, the package 110 may be a memory module, and the die 120 may comprise analog circuits.
As more and more integration takes place in system-in-package technology, thermal management may present a challenge. Conventional thermal management includes thermal vias in the package substrate 104, and the use of heat spreaders. However, for heat to escape from the die 120 to the package contacts 108, the heat flows from the die 120 through various materials in the package 110, the flip-chipped die 102, the underfill, and the package substrate 104, and through the package contacts 108 before escaping the system-in-package 124. It would be desirable to provide a system-in-package technology with efficient thermal pathways for heat to escape.